Bit-serial multipliers in various forms are discussed in detail by Smith and Denyer, `Serial-Data Computation`, Kluwer Academic Press, and particularly at pages 72 to 90. As discussed therein, serial-data multipliers have two principal architectures represented by the serial-pipeline multiplier, often called the Lyon multiplier, and the serial-parallel multiplier. The Lyon multiplier generally requires a greater area than the serial-parallel multiplier and although it exhibits somewhat better throughput, it exhibits a greater latency: in this context latency refers to the time between the appearance of the least-significant bit (LSB) at the input and the appearance of the LSB at the output. Two forms of serial-parallel multiplier exist: the flush multiplier, wherein the product bits are flushed out of a carry-save array in serial fashion, and the fractional multiplier, wherein the lower-order product bits are obtainable from a carry-save array and the higher order bits are provided by a residue adder including a parallel-in serial-out (PISO) pipe. The flush multiplier is simpler, but requires (m-1) guard bits in the data word, where m is the number of bits in the coefficient word. A fractional multiplier does not require such guard bits but requires additional circuitry between the partial product generators and the carry-save array to cope with the negative weight of the most-significant bit in twos-complement arithmetic. This additional circuitry renders the fractional serial/parallel multiplier significantly slower than the flush multiplier. This is important generally, but particularly so in digital signal processing involving short high-speed computational loops such as in recursive filters. However, it would be desirable to avoid both the use of guard bits and the disadvantages of additional circuitry in fractional serial/parallel multipliers.